The present invention relates generally to integrated circuit (IC) fabrication processes and, more particularly, to a multilayer dielectric stack, and a method for producing such a stack.
Current Si VLSI technology uses SiO2 as the gate dielectric in MOS devices. As device dimensions continue to scale down, the thickness of the SiO2 layer must also decrease to maintain the same capacitance between the gate and channel regions. Thicknesses of less than 2 nanometers (nm) are expected in the future. However, the occurrence of high tunneling current through such thin layers of SiO2 requires that alternate materials be considered. Materials with high dielectric constants would permit gate dielectric layers to be made thicker, and so alleviate the tunneling current problem. These so-called high-k dielectric films are defined herein as having a high dielectric constant relative to silicon dioxide. Typically, silicon dioxide has a dielectric constant of approximately 4, while it would be desirable to use a gate dielectric material with a dielectric constant of greater than approximately 10.
One common problem associated with the above-mentioned high-k dielectrics is that they develop a crystalline structure under normal integrated circuit manufacturing conditions. As a result, the surface of the film is very rough. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
Because of high direct tunneling currents, SiO2 films thinner than 1.5 nm generally cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts in the search for the replacement of SiO2, with TiO2 and Ta2O5 attracting the greatest attention. However, high temperature post deposition annealing, and the formation of an interfacial SiO2 layer, make achieving equivalent SiO2 thicknesses, also known as equivalent oxide thickness (EOT), of less than 1.5 nm very difficult.
It would be advantageous if an alternative dielectric that alleviated concerns about thin oxide films without degrading overall performance or increasing tunneling current could be used.
It would be advantageous if a high-k dielectric film could be used as an insulating barrier between a gate electrode and the underlying channel region in a MOS transistor.
It would be advantageous if high-k dielectric films could be formed with reduced surface roughness, crystallinity, and electrical leakage. It would be advantageous if these non-crystalline high dielectric constant materials could be used in gate dielectrics and storage capacitors of integrated circuits.
Accordingly, a multilayer dielectric stack composed of alternating layers of high-k material, which have high dielectric constants relative to silicon, and interposing material is provided. The high-k material is selected from titanium oxide (TiO2), zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), and barium and strontium titanium oxide ((Ba,Sr)TiO3), preferably zirconium oxide or hafnium oxide. The interposing material is selected from aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN or Si3N4), or silicon dioxide (SiO2), preferably aluminum oxide, aluminum nitride or silicon nitride.
Preferably, alternating layers of high-k material and interposing material replace prior art silicon dioxide dielectric layers in integrated circuits. Each layer is preferably between less than 50 angstroms thick. The thin layers of high-k material bounded by interposing material reduces or eliminates the formation of crystalline structures. The multiple layers reduce the tunneling current, which allows for better device performance. For a fixed total height, additional layers will reduce tunneling current. The overall capacitance of a given height stack will vary depending upon the dielectric constant of both the interposing material and the high-k material. The number of layers for a desired total thickness will be limited by the minimum thickness obtainable for each layer, and the device characteristics desired.
Also provided is an integrated circuit (IC) structure for an IC comprising a multilayer dielectric stack having a first layer of dielectric material overlying a semiconductor substrate, a second layer of dielectric material overlying the first layer, a third layer composed of the same material as the first layer overlying the second layer, and an electrode overlying the dielectric stack. The content of the dielectric stack is as described above. The overall thickness of the dielectric stack is preferably between 20 and 200 angstroms.
In another embodiment of the present invention, the integrated circuit structure is a MOS transistor comprising a gate electrode, a channel region having a top surface underlying the gate electrode, and a gate dielectric stack, which comprises a first dielectric layer comprising a first dielectric material, a second dielectric layer comprising a second dielectric material, and a third dielectric layer comprising the same material as the first dielectric layer, interposed between the gate electrode and the channel region top surface.
Some aspects of the invention further comprise an oxidation barrier interposed between the silicon substrate and the dielectric stack to prevent oxygen from migrating into the silicon substrate beneath the dielectric stack. The interface material is selected from the group consisting of aluminum nitride, silicon nitride, and silicon oxynitride.
In the fabrication of an IC on a semiconductor substrate having an upper surface, a method is provided to form a multilayer dielectric stack on the semiconductor substrate. The method comprises the steps of:
a) forming a first dielectric layer on the upper surface of the semiconductor substrate;
b) forming a second dielectric layer on the first dielectric layer; and
c) forming a third dielectric layer above the second dielectric layer, wherein the third dielectric layer comprises the same dielectric material as the first dielectric material.
Preferably, each dielectric layer is formed by atomic layer deposition, which is sometimes referred to as pulsed CVD, of a precursor followed by oxidation of the precursor to form the desired oxide material. Although atomic layer deposition is preferred, alternative methods of depositing each dielectric layer include sputtering and evaporation.
Following deposition of multiple dielectric layers, the entire dielectric stack is preferably annealed at temperatures between approximately 400 and 900 degrees Celsius to condition the stack, the interfaces between the layers, and the interface with the substrate.
Subsequent processing can be performed to complete the formation of the IC, including depositing an electrode layer and patterning the electrode layer and underlying multiple dielectric layers to form a multilayer dielectric stack structure.